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The 7135 A/D Converter

The ICL7135C and TLC7135C converters are manufactured with Texas Instruments highly efficient CMOS technology. These 4 1/2-digit, dual-slope-integrating, analog-to-digital converters (ADCs) are designed to provide interfaces to both a microprocessor and a visual display. The digit-drive outputs D1 through D4 and

multiplexed binary-coded-decimal outputs B1, B2, B4, and B8 provide an interface for LED or LCD decoder/drivers as well as microprocessors.

            The digit drive outputs D1, D2, D3, D4, D5 represent the 5 digits of the A/D conversion. When D5 is high the binary-coded-decimal outputs B1, B2, B4, and B8 give the BCD output for the most significant digit. Similarly when When D4 is high the binary-coded-decimal outputs B1, B2, B4, and B8 give the BCD output for the next most significant digit. This process goes on till the least significant digit after which the cycle continues. The BCD output for each digit is present at the output for 200 counts of the clock pulse. (refer timing diagram)

The ICL7135C and TLC7135C offer 50-ppm (one part in 20,000) resolution with a maximum linearity error of one count. The zero error is less than 10 µV and zero drift is less than 0.5 µV/°C. Source-impedance errors are minimized by low input current (less than 10 pA). Rollover error is limited to ±1 count. The BUSY, STROBE, RUN/HOLD, OVER RANGE, and UNDER RANGE control signals support microprocessor-based measurement systems. The control signals also can support remote data acquisition

systems with data transfer through universal asynchronous receiver transmitters (UARTs). The ICL7135C and TLC7135C are characterized for operation from 0...C to 70...C.

The digital data (in BCD format) is then fed to the PC through the Standard Printer Port (SPP). The registers and pinouts of the SPP are as follows

The Printer Port (SPP)

Registers (- unavailable)

IBM-PC Parallel Printer Port Female DB-25 Socket external Pin layout

 ______________________________________________________ 

/                                                      \

\  13  12  11  10   9   8   7   6   5   4   3   2   1  /

 \                                                    / 

  \  25  24  23  22  21  20  19  18  17  16  15  14  /  

   \________________________________________________/   

Pinouts

             Register  DB-25     I/O   

Signal Name    Bit      Pin   Direction

===========  ========  =====  =========

-Strobe        ¬C0       1      Output 

+Data Bit 0     D0       2      Output 

+Data Bit 1     D1       3      Output 

+Data Bit 2     D2       4      Output 

+Data Bit 3     D3       5      Output 

+Data Bit 4     D4       6      Output 

+Data Bit 5     D5       7      Output 

+Data Bit 6     D6       8      Output 

+Data Bit 7     D7       9      Output 

-Acknowledge    S6      10       Input 

+Busy          ¬S7      11       Input 

+Paper End      S5      12       Input 

+Select In      S4      13       Input 

-Auto Feed     ¬C1      14      Output 

-Error          S3      15       Input 

-Initialize     C2      16      Output 

-Select        ¬C3      17      Output 

 Ground          -     18-25       -   

(Note again that the S7, C0, C1 & C3 signals are inverted)

The Description of the IC’s used in the data acquisition system are as follows

1] The Octal D-type Transparent Latch IC 74HCT573

FEATURES

· Inputs and outputs on opposite sides of package allowing easy interface with microprocessors

· Useful as input or output port for microprocessors/microcomputers

· 3-state non-inverting outputs for bus oriented applications

· Common 3-state output enable input

· Functionally identical to the “563” and “373”

· Output capability: bus driver

· ICC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT573 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.

The 74HC/HCT573 are octal D-type transparent latches featuring separate D-type inputs for each latch and 3-state outputs for bus oriented applications.

A latch enable (LE) input and an output enable (OE) input are common to all latches.

The “573” consists of eight D-type transparent latches with 3-state true outputs. When LE is HIGH, data at the Dn inputs enter the latches. In this condition the latches are transparent,i.e. a latch output will change state each time its corresponding D-input

changes.

When LE is LOW the latches store the information that was present at the D-inputs a set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents of the 8 latches are available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the latches.

The “573” is functionally identical to the “563” and “373”, but the “563” has inverted outputs and the “373” has a different pin arrangement.

2] 3:8 Line Decoder / Demultiplexer IC 74HCT138

FEATURES

· Demultiplexing capability

· Multiple input enable for easy expansion

· Ideal for memory chip select decoding

· Active LOW mutually exclusive outputs

· Output capability: standard

· ICC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT138 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC

standard no. 7A. The 74HC/HCT138 decoders accept three binary weighted address inputs (A0 , A1 , A2 ) and when enabled, provide 8 mutually exclusive active LOW outputs (Y0 to Y7 ).

The “138” features three enable inputs: two active LOW (E1 and E2 ) and one active HIGH (E3 ). Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH.

This multiple enable function allows easy parallel expansion of the “138” to a 1-of-32 (5 lines to 32 lines) decoder with just four “138” ICs and one inverter. The ”138” can be used as an eight output demultiplexer by using one of the active LOW enable inputs as the data input and the remaining enable inputs as strobes. Unused enable inputs must be permanently tied to their appropriate active HIGH or LOW state. The ”138” is identical to the “238” but has inverting outputs.

3] ULN2803 Darlington Pair Transistor Array

FEATURES

• Eight darlingtons with common emitters.
• Output current of 500mA
• Output voltage of 50V
• Integral suppression diodes.
• Versions of all popular logic families.
• Output can be paralleled.
• Inputs pinned opposite outputs to simplify board layouts.

DESCRIPTION

The ULN2801A-ULN2805Aeach contain eight darlington transistors with common emitters and integral suppression diodes for inductive loads. Each darlington features a peak load current rating of 600mA (500mA continuous) and can withstand at least50V in the off state. Outputs may be paralleled for higher current capability. Five versions are available to simplify interfacing to standard logic families : the ULN2801Ais designed for general purpose applications with a current limit resistor ; theULN2802Ahas a 10.5kW inputresistor and zenerfor 14-25VPMOS; theULN2803Ahas a 2.7kW input resistor for 5V TTL and CMOS ; the ULN2804A has a 10.5kW input resistor for 6-15V CMOS and the ULN2805A is designed to sink a minimum of 350mA for standard and Schottky TTL where higher output current is required. All types are supplied in a 18-lead plastic DIP with a copper lead from and feature the convenient input opposite-output pinout to simplify board layout.

Data Acquisition System

            A Data Acquisition System is used to sample the required data in a systematic manner from the system into the PC. The above given data acquisition system will be utilizing the A/D converter IC7135. This converts the analog quantity to a proportional digital quantity.

            The output from the 7135 is in multiplexed BCD form. Hence to sample the data into the PC the data is demultiplexed using the circuit explained in the Control Card and Interface Card.          

            The 7135 A/D Converter is contained in each Digital readout meter ie AC voltmeter, DC voltmeter, AC ammeter, DC ammeter, Wattmeter.

            Each meter requires a dedicated Interface Card.

·        Specifications of the Interface Card are as follows.

1.      Inputs from ICL7135 :- bits D1-D5, bits B1-B8, BUSY, OVERRANGE, UNDERRANGE, POL, R/H.

2.      Input from Control Card:-  Connector K1 [ D, B, C, R/H]

3.      Output to Control Card :-  Connector P1 [B3, B4, B5, B6, B7]

The analog part of the 7135 circuit is different for different meters, hence it is not explained in detail. The function of the analog circuit is to produce a voltage proportional to the input applied to the meter. This proportional voltage must lie between –1.9999V DC and +1.9999V DC. Ideally the relation between the applied input and the output of the analog circuit must be linear throughout the range of the meter.

      The digital circuit includes three 8-bit latches (74HCT573) U11, U12, U13. the outputs form the input bus consisting of 5 bits. This bus is given as an input to the Control Card. The working is as follows

1.      When pin no.1 (D) is pulled low, output of U11 is activated. Hence bits D1-D5 are available on P1.

2.      When pin no.2 (B) is pulled low, output of U12 is activated. Hence bits D1-D5 are available on P1.

3.      When pin no.3 (C) is pulled low, output of U13 is activated. Hence bits D1-D5 are available on P1.

4.      When pin no.4 (R\H) is pulled low, output of 7135 is held at the previous reading. When this pin is pulled high, the A/D converter resumes the conversion cycles

.

THE CONTROL CARD

            The Control Card is an interface between the PC and the Test Bench. It not only provides acquisition but also control of the Test Bench.

            The Control circuit consists of 74HCT573 and ULN2803 (U1, U7, U6, U8). The Printer Port (J6) is used for communication between PC and the system.

            The Control Port of the Printer Port (pins 14, 16, 17) are fed to the input of the 3:8 decoder 74HCT138. The output of the decoder is active low and hence is inverted by use of NOT gates (74HC04). Each output can be activated by a particular address of the control port. The memory map of the outputs (Y₀- Y₇) is as given below in table 1.

CONTROL PORT MEMORY MAP

  Table 1

Interface Scan Logic

      Scanning of the multiplexed BCD output from the ICL7135 is done by sequentially scanning the D bits and then B bits and Control bits. The input is an 8-bit value. The memory map of the D, B, and C bits is as given below in table 2.

          I/P :-

Table 2

            The contents of the Control Bits are STROBE, OVERRANGE, UNDERRANGE, POLARITY and BUSY. These bits are polled by the software to check the status of the ICL7135 and the status of the digital output.

            The D bits indicate which digit’s output is carried on the B bits. So when D5 is high, the BCD output at B bits is the BCD equivalent of the most significant digit. When D4 is high, the BCD output at B bits is the BCD equivalent of the next most significant digit. This procedure continues till all the digits are aquired.

            To get the exact BCD equivalent, the B bits must be bitwise anded with 80_H and the result is bitwise shifted to the right by 4 bit positions.

                The acquisition system under consideration can aquire data from 8 digital meters utilizing the ICL7135. To select a particular meter, the D, B, C bits pertaining to that particular meter must be activated and inputted.

            Each D, B, C bits has two addresses one for Control Port and other for Data Port. The Control Port address selects a particular latch (U16, U17, U20 and U19). The Data Port address selects one particular line transparent to the input port.

 The memory map of the D, B, C bits for all the meters are as given below in table 3.

 INTERFACE MEMORY MAP

Table 3

RELAY CONTROL

          The relays are used to activate the contactors in the Test Bench. Relays are controlled by the control card. Relay Card 1 or Relay Card 2 can be selected by control port address. Relays 1-8 can be controlled by sending appropriate bits on the data port after activating U1. same is followed for Relays 9-16 after activating U7.

When a high bit is sent on the line, the relay turns ON. Similarly when a low bit is sent the relay turns OFF.

The memory map of all the 24 relays is as shown in table 4

RELAYS :-

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